1. Field of the Invention
The present invention relates generally to RAID storage controllers and in particular to a single chip integrated circuit which provides full RAID functionality along with a substantial decrease in complexity and associated costs.
2. Discussion of Related Art
RAID storage subsystems are known to provide high storage capacity, fast storage access, and highly reliable operation. In general, RAID subsystems comprise an array of inexpensive disk drives operated by a RAID controller which presents the array to attached host systems as though operating as a single large, fast, reliable single disk drive. The RAID controller maps requests from attached host systems into appropriate requests to the array of disk drives.
Many current RAID controllers implement various, if not all, of the presently popular RAID architectures. Referred to as RAID levels 0 through 5, each RAID architecture utilizes the array of disk drives in a manner to provide enhanced performance and reliability. The various RAID levels correspond to varying geometries in the configuration of the disk drives of the disk array. For example, a simple RAID 1 configuration calls for exact mirroring of the contents of a first disk drive on a parallel or mirrored second drive. This architecture does not affect performance of the subsystem in any appreciable manner but does enhance reliability of the data storage. RAID level 5 by contrast entails a more complex mapping of the data on the disk array. Host supplied data is distributed over a plurality of drives in the disk array. This feature diminishes subsystem reliability but enhances performance by utilizing parallel transfers of data over multiple I/O channels to multiple disk drives. To restore required reliability, RAID level 5 uses redundancy information stored on another drive in the disk array. The redundancy information is used to recover lost data in case of failure of one of the disk drives in the disk array.
Addition of the redundancy (e.g., parity) data to recover reliability imposes a performance cost on the RAID controller by requiring the update of redundancy (e.g., parity) information in response to updates of the associated data. To reduce the negative performance impact of this well known RAID write penalty, most RAID controllers utilize significant amounts of cache memory to buffer write operations and thereby reduce the perceived performance impact of maintaining redundancy information.
As RAID features have evolved and performance demands have increased, RAID controllers have grown into large, complex, and hence costly devices. Typical RAID controllers comprise a printed circuit board with a general purpose processor, RAM and ROM devices for storage of operating code and variables, and I/O interface controllers for connection to attached hosts systems and connected disk drives. High performance RAID controllers increase the amount of cache memory and add custom circuits for DMA transfers and/or parity computation assist.
It is presently common for personal computer system main boards (e.g., motherboards) to incorporate storage controllers. Such motherboard integration further reduces costs and complexity by reducing the needs for connectors and external bus connections between the storage controller and related motherboard devices.
As demand for high performance, high reliability RAID storage increases, so increases the demand for lower cost RAID controller solutions. It is evident from the above that a need exists for a simpler, lower cost RAID controller architecture to enable lower cost and complexity associated with high performance and high reliability storage subsystems. In particular it is evident from the above that a need exists for a highly integrated RAID storage controller which can be easily integrated with personal computer or workstation motherboards.